----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    17:19:41 06/06/2010 
-- Design Name: 
-- Module Name:    AD_Control - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity AD_Control is
    Port ( load_in : in  STD_LOGIC;
           load_ok_out : out  STD_LOGIC;
           ram_data_in : in  STD_LOGIC_VECTOR (31 downto 0);
           ram_adr_out : out  STD_LOGIC_VECTOR (11 downto 0);
           ram_we : out  STD_LOGIC;
           ram_enable : out  STD_LOGIC;
           ad_divider_out : out  STD_LOGIC_VECTOR (7 downto 0);
           ad_n_samples_out : out  STD_LOGIC_VECTOR (11 downto 0);
           ad_n_presamples_out : out  STD_LOGIC_VECTOR (11 downto 0);
           ad_trigger_a_b_out : out  STD_LOGIC;
           ad_trigger_mode_out : out  STD_LOGIC;
           ad_trigger_edge_out : out  STD_LOGIC;
           ad_trigger_level_out : out  STD_LOGIC_VECTOR (11 downto 0);
           ad_enable_out : out  STD_LOGIC;
           ad_reset_out : out  STD_LOGIC;
           ram_clk : out  STD_LOGIC;
			  clk_in: in  STD_LOGIC;
			  ad_enable_in : in STD_LOGIC);
end AD_Control;

architecture Behavioral of AD_Control is

begin
P1:process (clk_in)
variable state : STD_LOGIC_VECTOR(3 downto 0) := "0000";
variable loadPos : STD_LOGIC := '0';
begin

	if rising_edge(clk_in) then
	
		if state = "0000" then
			ad_reset_out <= '1';
			if load_in = '1' then 
				state := "0001";
				ad_reset_out <= '1';
				load_ok_out <= '0';
			elsif(ad_enable_in = '1') then 
				ad_enable_out <= '1'; 
				ad_reset_out <= '0';
			end if;
			
		elsif state = "0001" then
		ad_reset_out <= '1';
		ad_enable_out <= '0';
		ram_adr_out <=  "000000000000"; -- Sample Rate Divider
		ram_enable <= '1';
		state := "0010";
		
		elsif state = "0010" then
		ram_adr_out <=  "000000000001"; -- Number of Samples
		state := "0011";
		ad_divider_out <= ram_data_in(7 downto 0);
		
		elsif state = "0011" then
		ram_adr_out <=  "000000000010"; -- Number of Pre-Samples
		state := "0100";
		ad_n_samples_out <= ram_data_in(11 downto 0);
		
		elsif state = "0100" then
		ram_adr_out <=  "000000000011"; -- Trig A/B
		state := "0101";
		ad_n_presamples_out <= ram_data_in(11 downto 0);
		
		elsif state = "0101" then
		ram_adr_out <=  "000000000100"; -- Trig Mode
		state := "0110";
		ad_trigger_a_b_out <= ram_data_in(0);
		
		elsif state = "0110" then
		ram_adr_out <=  "000000000101"; -- Trig Edge
		state := "0111";
		ad_trigger_mode_out <= ram_data_in(0);
				
		elsif state = "0111" then
		ram_adr_out <=  "000000000110"; -- Trig Level
		state := "1000";
		ad_trigger_edge_out <= ram_data_in(0);	

		elsif state = "1000" then
		state := "0000";
		ad_trigger_level_out <= ram_data_in(11 downto 0);
	   load_ok_out <= '1';		
		
				
		end if;
		
	end if;
	ram_clk <= clk_in;
	ram_we <= '0';
end process;

end Behavioral;

